Intel to Create RISC-V Development Platform with SiFive P550 Cores on 7nm in 2022
by Dr. Ian Cutress on June 22, 2021 9:01 AM EST
As part of SiFive’s announcements today, along with enabling SiFive IP on Intel’s Foundry Service offerings, Intel will be creating its own RISC-V development platform using its 7nm process technology. This platform, called Horse Creek, will feature several of SiFive’s new Performance P550 cores also being announced today, and will be paired with Intel’s DDR and PCIe IP technology.
On first reading into the press release, it isn’t 100% clear that Intel’s commentary discusses a platform with P550 as a host or as an add-in device: to quote Intel, ‘We are pleased to be a lead development partner with SiFive to showcase to mutual customers the impressive performance of their P550 on our 7nm Horse Creek platform’. Intel historically typically keeps its Creek family names, such as Boulder Creek, Cherry Creek, or Timber Creek, for socketed platforms - not for all-in-one embedded development platforms. Not only that, the wording makes it sound like we should consider a RISC-V core as an assistant core managing another part of a system.
However it would appear that Intel intends to make this a fully-featured development system, along similar lines to SiFive’s own HiFive Unmatched platform launched early this year. What makes this special is that Intel is committing to developing the SoC on its own 7nm process node, which provides a ‘simpler’ vehicle for Intel to test and ramp up its 7nm technology. This can be coupled with increasing interest in RISC-V development, and deploying a platform though Intel’s supply chain and distribution might have a far reach to put these in the hands of upcoming developers.
The new SiFive Performance P550 core at the heart of Horse Creek is SiFive’s highest performance processor to date, with the company quoting a SPEC2006int of 8.65 per GHz. It is a Linux-capable core, with full support for the RISC-V vector extension v1.0rc. It has a 13-stage triple-issue out-of-order microarchitecture with a private 32KB+32KB L1 cache and a private L2 cache (per core) The design supports four cores in a single cluster that can be paired up to 4 MB of shared L3.
The time scale for this platform coming to market is quite interesting. Despite Intel recently committed to bringing its 7nm to market in 2023 with the compute tile for its Meteor Lake processor as its first 7nm product, we’re being told that Horse Creek silicon will be ready in 2022, which would make Horse Creek its first 7nm product. For what it is worth, it’s unlikely that the Intel RISC-V solution is tile-based, but it might be easy enough to bring a small RISC-V chip development platform to market around then. The chip is likely to be small, so that might work in favor of its costs as well. A question does remain as to whether Intel’s involvement here is purely in the hardware, or whether there will be an Intel-based software stack to go along with it.
Related Reading
- Samsung to Use SiFive RISC-V Cores for SoCs, Automotive, 5G Applications
- SiFive Announces First RISC-V OoO CPU Core: The U8-Series Processor IP
- SiFive Acquires USB 2.0 and 3.x IP Portfolio to Strengthen RISC-V SoCs
- SiFive Unveils Freedom Platforms for RISC-V-Based Semi-Custom Chips
- Western Digital’s RISC-V "SweRV" Core Design Released For Free
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SarahKerrigan - Tuesday, June 22, 2021 - link
Considering the comparison point is Cortex-A75, this still puts top-end RV apps cores a long way behind top-end ARM licensables. But they certainly seem to be improving.Also, Doc Ian, it looks like in the last paragraph you refer to Horse Creek as Horse Ridge, which is a very different product (quantum control circuit.) I assume this is just a typo, since it's sorta baffling otherwise.
Ian Cutress - Tuesday, June 22, 2021 - link
I've written Horse Ridge so often, it's in my brain. Fixed that up.FreckledTrout - Tuesday, June 22, 2021 - link
Schrödinger's Horse :)eastcoast_pete - Wednesday, June 23, 2021 - link
Doesn't help that some will now say that Intel's future is indeed "up the creek (s)".eastcoast_pete - Wednesday, June 23, 2021 - link
Although the RV "performance core" appears to be much closer to ARM's LITTLE cores in size/area/transistor count. And, unlike them, it's OOO, something ARM has been resistant to implementing even in their newest designs.Small Bison - Tuesday, June 22, 2021 - link
“The new SiFive Performance P550 core at the heart of Horse Creek is SiFive’s highest performance processor to date, with the company quoting a SPEC2006int of 8.65 per GHz.”How does this compare against other common CPU designs? I think it would be useful to have that info in the article.
SarahKerrigan - Tuesday, June 22, 2021 - link
Sifive is saying the comparison point is the Cortex-A75. That makes it fairly fast by the standard of apps processors as a whole, but far behind current ARM licensable IP or mainstream cores from Intel, AMD, or Apple.brucehoult - Tuesday, June 22, 2021 - link
Four years and one month behind A75 announcement, to be precise.The U84 was announced 4.75 years after the A72. The U74 was announced 6 years after the A53.
So far, each generation of SiFive cores is about one less year behind ARM than the previous one.
Remembering that SiFive was founded after the A72 was announced.
Ian Cutress - Tuesday, June 22, 2021 - link
We've been publishing graphs with this data for a while.https://www.anandtech.com/show/16226/apple-silicon...
https://www.anandtech.com/show/16214/amd-zen-3-ryz...
A13 scores 19.85/GHz
A14 scores 21.1/GHz
R9 5950X scores 13.57/GHz
i9-10900K scores 11.08/GHz
P550 is probably peak score/GHz, whereas all of these points are at the most extreme/least efficient point for the high-end products. The overall performance also matters when you factor in frequency, as cores won't scale linearly with core frequency as other parts of the SoC will be fixed.
brucethemoose - Tuesday, June 22, 2021 - link
I wonder if cloud vendors would be interested in a giant package stuffed full of these cores? Small, isolated VMs don't need tons of core-cluster to core-cluster communication.I understand this design probably can't do that... and if there was interest, I suppose Altera or someone would've come out with a design based on smaller ARM cores.