Intel Announces D7-P5500 and D7-P5600 Series PCIe 4.0 Enterprise SSDs

Intel has yet to launch their first CPUs supporting PCIe 4.0, but other parts of the business are keeping pace with the transition: network controllers, FPGAs, and starting today, SSDs. The first PCIe 4.0 SSDs from Intel are based on their 96-layer 3D TLC NAND flash memory, slotting into Intel's product line just below Optane products and serving as Intel's top tier of flash-based SSDs. The new Intel D7-P5500 and D7-P5600 are codenamed Arbordale Plus, a codename Intel revealed last fall without providing any other information except that the original Arbordale product was never released.

The two new SSD product lines are the first to fall into the D7 tier under the new naming scheme adopted by Intel in 2018. The P5500 and P5600 are closely-related products that differ primarily in their overprovisioning ratios and consequently their usable capacities, write speed and write endurance. The P5500 is the 1 drive write per day (DWPD) lineup with capacities ranging from 1.92 TB up to 7.68 TB, while the P5600 is the 3 DWPD tier with capacities from 1.6 TB to 6.4 TB. These serve as the successors to the P4510 and P4610 Cliffdale Refresh drives, and as such we expect some follow-on models to introduce the EDSFF form factor options and QLC-based drives that are still due for an update.

The switch to PCIe 4.0 enables a big jump in maximum throughputs supported: from 3.2 GB/s up to 7 GB/s for sequential reads, while sequential writes show a more modest increase from 3.2 GB/s to 4.3 GB/s. Random reads now hit 1M IOPS compared to about 651k IOPS from the previous generation, and random writes are still bottlenecked by the flash itself with a peak of 260k IOPS from the new P5600.

Intel hasn't shared information about the internal architecture of the new SSDs, so we don't know if they're still using a 12-channel controller design like their previous generation. Intel does tout improved QoS and a handful of new features, including a re-working of their TRIM implementation to reduce its interference with the performance of more important IO commands.

Related Reading

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• Intel Shares New Optane And 3D NAND Roadmap - Barlow Pass DIMMs & 144L QLC NAND in 2020